Trinamics Beheer B.V.

Senior VHDL Design Engineer – Trinamics Beheer B.V. – Almelo

Jobid=534435462599673830 (0.0497)

Functieomschrijving

  • Design, simulate, implement, and verify
    FPGA circuits using VHDL
  • Work closely with
    hardware and embedded software teams to align
    specifications
  • Participate in project teams to
    develop advanced electronic systems
  • Visit
    clients occasionally for technical discussions and system
    integration
  • Ensure all FPGA components meet
    quality and performance standards
  • Document
    your work thoroughly and provide technical input to
    stakeholders

Functie-eisen

  • A completed Bachelor’s or Master’s degree in Electrical
    Engineering or Electronics
  • At least 8 years of
    experience with VHDL design for product development
  • Proven skills in writing clean, maintainable VHDL
    code
  • Experience with simulation tools, test
    benches, and measurement equipment
  • Knowledge
    of digital components like FPGAs, CPLDs, and standard interfaces
    (SPI, I2C, etc.)
  • Familiarity with tools from
    Intel, Xilinx, or Lattice is a plus
  • Solid
    communication skills in English for documentation and
    collaboration

Arbeidsvoorwaarden

  • A permanent position through Trinamics –
    no temporary projects
  • The possibility of a
    permanent contract with our client
  • A
    competitive monthly salary between €5.500,00 and €7.500,00 (incl.
    8% holiday allowance), based on experience
  • 27
    vacation days + 13 ADV days for a healthy work-life
    balance
  • Flexible working hours with the option
    to plan your day around your life
  • A dynamic
    environment where your ideas and initiative are
    appreciated
  • Extensive personal development
    opportunities through training, workshops, and coaching
  • A flat and informal culture where entrepreneurship is
    recognized and encouraged

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