Senior VHDL Design Engineer – Trinamics Beheer B.V. – Almelo

  • Almelo

Trinamics Beheer B.V.


As a Senior VHDL Design Engineer with Benchmark, you’ll grow in Electrical Engineering. In a global team, you contribute to building complete (sub-)systems, taking charge of designing, implementing, and verifying these systems.

  • You oversee the design, simulation, implementation, and verification of FPGA circuits, employing VHDL code. Your collaboration extends to other disciplines, including hardware and embedded software development.


  • Completed Bachelor or Master in Electrical & Electronics Engineering.
  • Minimum of 8 years of experience in VHDL design within productdevelopment (Intel, Xilinx, Lattice)
  • You bring experience in utilizing simulation tools and measurement equipment for digital circuits, including FPGAs, CPLDs, and standard interfaces like SPI and I2C.
  • Fluent in English


In addition to a competitive salary (75k-85k), we provide outstanding benefits such as:

  • 27 vacation days and 13 ATV days.
  • Holiday allowance
  • Flexible working hours, allowing you to arrange your schedule, ensuring completion of your work.
  • Quarterly bonus based on revenue (up to 5%)

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